ADUM5402WCRWZ【PDF 23/24 页】IC ISOLATOR 4CH DCDC CONV 16SOIC

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Data Sheet

RATED PEAK VOLTAGE

0V

Figure 28. Bipolar AC Waveform

RATED PEAK VOLTAGE

ADuM5401W/ADuM5402W/ADuM5403W

Symptom

The V ISO output voltage restarts to an incorrect voltage between

3.4 V and 4.7 V when power is removed at V DD1 and then reapplied

between 250 ms and 3 sec later. The error occurs only on restart; it

does not occur at initial power-up. If the part initializes incorrectly,

power must be removed for an extended time to allow internal

nodes to discharge and reset. The amount of time required can

0V

Figure 29. DC Waveform

be several minutes at low temperature; therefore, it is critical to

avoid allowing the device to initialize improperly.

Cause

RATED PEAK VOLTAGE

0V

NOTES

1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION

PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE

WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE.

THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE

VOLTAGE CANNOT CROSS 0V.

Figure 30. Unipolar AC Waveform

V ISO START-UP ISSUES

An issue with reliable startup was identified in the ADuM5401W/

ADuM5402W/ADuM5403W components. This issue has been

addressed in the ADuM5401W-1/ADuM5402W-1/ADuM5403W-

1 for the current silicon. The ADuM5401W-1/ADuM5402W-1/

ADuM5403W-1 devices are recommended for all new designs.

The following description applies only to the original released

version of these devices. Production of the original release of

the devices is being continued for existing customers, but it is

not recommended for new designs.

The secondary side band gap reference does not initialize to the

proper voltage due to a slow slew rate on V ISO after the internal

nodes are precharged during the previous power cycle. The

secondary side band gap sets the output voltage of the regulator.

Solution

The slew rate of V ISO is determined by the resistive and capacitive

load present on the output. Designs that attempt to reduce ripple

by adding capacitance to the V ISO output can slow the slew rate

enough to cause start-up errors. Choose values for bulk capacitance

based on the effective dc load. Calculate the dc load as the resistive

equivalent to the current drawn from the V ISO line. Determine

the range of allowable capacitance for the V ISO output from

Figure 31. Choose the bulk capacitance for V ISO to achieve the

application required ripple, unless the value is in the disallowed

combinations area; then the value must be reduced to avoid

restart issues.

100k

10k

The start-up issue in the original release of the ADuM5401W/

ADuM5402W/ADuM5403W is related to initialization of the

band gap voltage references on the primary (power input) and

secondary (power output) sides of the iso Power device and are

being addressed in future revisions of the silicon. For current

versions of the silicon, the user must follow these design guide-

lines to guarantee proper operation of the device.

The band gap voltage references are vulnerable to slow power-up

slew rate. The susceptibility to power-up errors is process sensitive;

1k

100

10

1

DISALLOWED

COMBINATIONS

therefore, not all devices display these behaviors. These recommen-

dations should be implemented for all designs until the corrections

are made to the silicon. The symptoms and corrective actions

required for issues with the primary and secondary side startup

are different.

Rev. D | Page 23 of 24

1 10 100

C VISO (μF)

Figure 31. Maximum Capacitive Load for Proper Restart

1k

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